View LT3013B_354916.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LT3013B 250mA, 4V to 80V Low Dropout Micropower Linear Regulator with PWRGD
FEATURES

DESCRIPTIO
Wide Input Voltage Range: 4V to 80V Low Quiescent Current: 65A Low Dropout Voltage: 400mV Output Current: 250mA No Protection Diodes Needed Adjustable Output from 1.24V to 60V Stable with 3.3F Output Capacitor Stable with Aluminum, Tantalum or Ceramic Capacitors Reverse-Battery Protection No Reverse Current Flow from Output to Input Thermal Limiting Thermally Enhanced 16-Lead TSSOP and 12 Pin (4mm x 3mm) DFN Package
The LT(R)3013B is a high voltage, micropower low dropout linear regulator. The device is capable of supplying 250mA of output current with a dropout voltage of 400mV. Designed for use in battery-powered or high voltage systems, the low quiescent current (65A operating) makes the LT3013B an ideal choice. Quiescent current is also well controlled in dropout. Other features of the LT3013B include a PWRGD flag to indicate output regulation. The delay between regulated output level and flag indication is programmable with a single capacitor. The LT3013B also has the ability to operate with very small output capacitors. The regulator is stable with only 3.3F on the output while most older devices require between 10F and 100F for stability. Small ceramic capacitors can be used without any need for series resistance (ESR) as is common with other regulators. Internal protection circuitry includes reverse-battery protection, current limiting, thermal limiting and reverse current protection. The device is available with an adjustable output with a 1.24V reference voltage. The LT3013B regulator is available in the thermally enhanced 16-lead TSSOP and the low profile (0.75mm), 12 pin (4mm x 3mm) DFN package, both providing excellent thermal characteristics.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

Low Current High Voltage Regulators Regulator for Battery-Powered Systems Telecom Applications Automotive Applications
TYPICAL APPLICATIO
IN VIN 5.4V TO 80V 1F 1.6M PWRGD GND ADJ CT OUT LT3013B
400
5V Supply
DROPOUT VOLTAGE (mV)
VOUT 5V 250mA 3.3F
350 300 250 200 150 100 50 0 0 50 100 150 200 OUTPUT CURRENT (mA) 250
3013 TA02
750k
249k
3013 TA01
1000pF
U
Dropout Voltage
3013bfa
U
U
1
LT3013B
ABSOLUTE
(Note 1)
AXI U
RATI GS
Storage Temperature Range TSSOP Package ........................... -65C to 150C DFN Package ............................... -65C to 125C Operating Junction Temperature Range (Notes 3, 9, 10) ........................... -40C to 125C Lead Temperature (FE16 Soldering, 10 sec) ... 300C
IN Pin Voltage ................................................... 80V OUT Pin Voltage ............................................... 60V IN to OUT Differential Voltage ........................... 80V ADJ Pin Voltage .................................................. 7V CT Pin Voltage ........................................... 7V, -0.5V PWRGD Pin Voltage ................................ 80V, -0.5V Output Short-Circuit Duration ..................... Indefinite
PACKAGE/ORDER I FOR ATIO
TOP VIEW NC OUT OUT ADJ GND PWRGD 1 2 3 13 4 5 6 9 8 7 NC NC CT 12 NC 11 IN 10 IN
DE PACKAGE 12-LEAD (4mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 40C/ W, JC = 16C/ W EXPOSED PAD (PIN13) IS GND MUST BE SOLDERED TO PCB
ORDER PART NUMBER LT3013BEDE
DE PART MARKING 3013B
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C.
PARAMETER Minimum Input Voltage ADJ Pin Voltage (Notes 2,3) Line Regulation Load Regulation (Note 2) CONDITIONS ILOAD = 250mA VIN = 4V, ILOAD = 1mA 4.5V < VIN < 80V, 1mA < ILOAD < 250mA VIN = 4V to 80V, ILOAD = 1mA (Note 2) VIN = 4.5V, ILOAD = 1mA to 250mA VIN = 4.5V, ILOAD = 1mA to 250mA

2
U
U
W
WW
U
W
TOP VIEW GND NC OUT OUT ADJ GND PWRGD GND 1 2 3 4 5 6 7 8 17 16 GND 15 NC 14 IN 13 IN 12 NC 11 NC 10 CT 9 GND
FE PACKAGE 16-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 40C/ W, JC = 16C/ W EXPOSED PAD (PIN17) IS GND MUST BE SOLDERED TO PCB
ORDER PART NUMBER LT3013BEFE
FE PART MARKING 3013BEFE
MIN 1.225 1.2
TYP 4 1.24 1.24 0.1 7
MAX 4.5 1.255 1.28 5 12 25
UNITS V V V mV mV mV
3013bfa
LT3013B
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C.
PARAMETER Dropout Voltage VIN = VOUT(NOMINAL) (Notes 4, 5) CONDITIONS ILOAD = 10mA ILOAD = 10mA ILOAD = 50mA ILOAD = 50mA ILOAD = 250mA ILOAD = 250mA GND Pin Current VIN = 4.5V (Notes 4, 6) Output Voltage Noise ADJ Pin Bias Current PWRGD Trip Point PWRGD Trip Point Hysteresis PWRGD Output Low Voltage CT Pin Charging Current CT Pin Voltage Differential Ripple Rejection Current Limit Reverse Output Current (Note 8) VCT(PWRGD High) - VCT(PWRGD Low) VIN = 7V(Avg), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = 250mA VIN = 7V, VOUT = 0V VIN = 4.5V, VOUT = -0.1V (Note 2) VOUT = 1.24V, VIN < 1.24V (Note 2) 65 270 12 25 ILOAD = 0mA ILOAD = 100mA ILOAD = 250mA COUT = 10F, ILOAD = 250mA, BW = 10Hz to 100kHz (Note 7) % of Nominal Output Voltage, Output Rising % of Nominal Output Voltage IPWRGD = 50A

MIN
TYP 160 250
MAX 230 300 340 420 490 620 120 18 100 94 250 6
UNITS mV mV mV mV mV mV A mA mA VRMS nA % % mV A V dB mA mA A
400

65 3 10 100 30 85 90 1.1 140 3.6 1.6 75 400
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3013B is tested and specified for these conditions with the ADJ pin connected to the OUT pin. Note 3: Operating conditions are limited by maximum junction temperature. The regulated output voltage specification will not apply for all possible combinations of input voltage and output current. When operating at maximum input voltage, the output current range must be limited. When operating at maximum output current, the input voltage range must be limited. Note 4: To satisfy requirements for minimum input voltage, the LT3013B is tested and specified for these conditions with an external resistor divider (249k bottom, 549k top) for an output voltage of 4V. The external resistor divider will add a 5A DC load on the output. Note 5: Dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output current. In dropout, the output voltage will be equal to (VIN - VDROPOUT).
Note 6: GND pin current is tested with VIN = 4.5V and a current source load. This means the device is tested while operating close to its dropout region. This is the worst-case GND pin current. The GND pin current will decrease slightly at higher input voltages. Note 7: ADJ pin bias current flows into the ADJ pin. Note 8: Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output voltage. This current flows into the OUT pin and out the GND pin. Note 9: The LT3013BE is guaranteed to meet performance specifications from 0C to 125C operating junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. Note 10: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
3013bfa
3
LT3013B
TYPICAL PERFOR A CE CHARACTERISTICS
Typical Dropout Voltage
600
GUARANTEED DROPOUT VOLTAGE (mV)
500
TJ = 125C
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
400 300 200 100 0 TJ = 25C
0
50
100 150 200 OUTPUT CURRENT (mA)
600 500
Quiescent Current
1.260 1.255
DROPOUT VOLTAGE (mV)
400 300
IL = 100mA
ADJ PIN VOLTAGE (V)
IL = 250mA
1.250 1.245 1.240 1.235 1.230 1.225
QUIESCENT CURRENT (A)
IL = 50mA
200
IL = 10mA
100 0 -50
IL = 1mA
-25
50 25 0 75 TEMPERATURE (C)
GND Pin Current
1.2 1.0 TJ = 25C *FOR VOUT = 1.24V 10 9 8
GND PIN CURRENT (mA)
GND PIN CURRENT (mA)
0.8 0.6 0.4 0.2 0
7 6 5 4 3 2 1
GND PIN CURRENT (mA)
RL = 49.6 IL = 25mA* RL = 124 IL = 10mA*
RL = 1.24k IL = 1mA*
0
1
2
34567 INPUT VOLTAGE (V)
4
UW
3013 G01
Guaranteed Dropout Voltage
600 500 400 300 200 100 0 0 50 150 100 200 OUTPUT CURRENT (mA) 250
3013 G02
Dropout Voltage
600 500 400 300 IL = 50mA 200 IL = 10mA 100 0 -50 -25 IL = 1mA 50 25 0 75 TEMPERATURE (C) 100 125 IL = 250mA IL = 100mA
= TEST POINTS
TJ 125C
TJ 25C
250
3013 G03
ADJ Pin Voltage
IL = 1mA 80 70 60 50 40 30 20 10 0 50 75 25 TEMPERATURE (C) 100 125 0
Quiescent Current
TJ = 25C RL =
100
125
1.220 - 50 - 25
0
1
2
34567 INPUT VOLTAGE (V)
8
9
10
3013 G03
3013 G05
3013 G06
GND Pin Current
TJ = 25C, *FOR VOUT = 1.24V 10
GND Pin Current vs ILOAD
VIN = 4.5V 9 TJ = 25C 8 7 6 5 4 3 2
RL = 4.96 IL = 250mA*
RL = 12.4 IL = 100mA*
RL = 24.8, IL = 50mA* 0 1 2 34567 INPUT VOLTAGE (V) 8 9 10
1 0 0 50 100 150 200 LOAD CURRENT (mA) 250
3013 G09
8
9
10
0
3013 G07
3013 G08
3013bfa
LT3013B TYPICAL PERFOR A CE CHARACTERISTICS
ADJ Pin Bias Current
PWRGD TRIP POINT (% OF OUTPUT VOLTAGE)
50 45 95 94 93 92 91 90 89 88 87 86 85 - 50 - 25 0 50 75 25 TEMPERATURE (C) 100 125 OUTPUT FALLING OUTPUT RISING
PWRGD OUTPUT LOW VOLTAGE (mV)
ADJ PIN BIAS CURRENT (nA)
40 35 30 25 20 15 10 5 0 - 50 - 25 0 50 75 25 TEMPERATURE (C) 100 125
CT Charging Current
4.0 3.5 PWRGD TRIPPED HIGH 2.0
CT COMPARATOR THRESHOLDS (V)
CT CHARGING CURRENT (A)
3.0 2.5 2.0 1.5 1.0 0.5 0 - 50 - 25 0 50 75 25 TEMPERATURE (C) 100 125
1.2 1.0 0.8 0.6 0.4 0.2 0 - 50 - 25 0 VCT (LOW) 50 75 25 TEMPERATURE (C) 100 125
CURRENT LIMIT (A)
Current Limit
0.7
REVERSE OUTPUT CURRENT (A)
CURRENT LIMIT (A)
0.5 0.4 0.3 0.2 0.1 VIN = 7V VOUT = 0V 50 25 0 75 TEMPERATURE (C) 100 125
REVERSE OUTPUT CURRENT (A)
0.6
0 -50 -25
UW
3013 G13 3013 G27 3013 G15
PWRGD Trip Point
200 180 160 140 120 100 80 60 40 20
PWRGD Output Low Voltage
IPWRGD = 50A
0 - 50 - 25
0
50 75 25 TEMPERATURE (C)
100
125
3013 G25
3013 G26
CT Comparator Thresholds
1.0 VCT (HIGH) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.8 1.6 1.4
Current Limit
VOUT = 0V
TJ = 25C TJ = 125C
0
10
20
30 40 50 60 INPUT VOLTAGE (V)
70
80
3013 G28
3013 G14
Reverse Output Current
200 TJ = 25C 180 VIN = 0V VOUT = VADJ 160 140 120 100 80 60 40 20 0 0 1 2 345678 OUTPUT VOLTAGE (V) 9 10 CURRENT FLOWS INTO OUTPUT PIN ADJ PIN CLAMP (SEE APPLICATIONS INFORMATION) 35 30 25 20 15 10 5
Reverse Output Current
VIN = 0V VOUT = VADJ = 1.24V
0 - 50 - 25
0
75 50 25 TEMPERATURE (C)
100
125
3013 G16
3013 G17
3013bfa
5
LT3013B TYPICAL PERFOR A CE CHARACTERISTICS
Input Ripple Rejection
92 88
RIPPLE REJECTION (dB)
80 84 80 76 72 68 64 VIN = 4.5V + 0.5VP-P RIPPLE AT f = 120Hz IL = 250mA VOUT = 1.24V 50 25 0 75 TEMPERATURE (C) 100 125
RIPPLE REJECTION (dB)
MINIMUM INPUT VOLTAGE (V)
60 -50 -25
Load Regulation
OUTPUT NOISE SPECTRAL DENSITY (V/Hz)
0 -2
LOAD REGULATION (mV)
IL = 1mA TO 250mA
-4 -6 -8 -10 -12 -14 -16 -18 -20 - 50 - 25 0 75 50 25 TEMPERATURE (C) 100 125
10Hz to 100kHz Output Noise
0.15
OUTPUT VOLTAGE DEVIATION (V)
VOUT 100V/DIV
LOAD CURRENT (mA)
COUT = 10F IL = 250mA VOUT = VADJ
6
UW
3013 G18
Input Ripple Rejection
100 VIN = 4.5V + 50mVRMS RIPPLE 90 ILOAD = 250mA
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
Minimum Input Voltage
ILOAD = 250mA
70 60 50 40 30 20 10 0 10 100 1k 10k FREQUENCY (Hz) 100k 1M
3013 G19
COUT = 10F
COUT = 3.3F
0 - 50 - 25
0
50 75 25 TEMPERATURE (C)
100
125
3013 G20
Output Noise Spectral Density
10 COUT = 3.3F ILOAD = 250mA
1
0.1
0.01 10 100 1k 10k FREQUENCY (Hz) 100k
3013 G22
3013 G21
Transient Response
0.10 0.05 0 -0.05 -0.10 -0.15 300 200 100 0 0 100 300 200 TIME (s) 400 500
3013 G24
VIN = 6V VOUT = 5V CIN = 3.3F CERAMIC COUT = 3.3F CERAMIC ILOAD = 100mA TO 200mA
1ms/DIV
3013B G23
3013bfa
LT3013B
PI FU CTIO S
OUT (Pins 2, 3)/(Pins 3, 4): Output. The output supplies power to the load. A minimum output capacitor of 3.3F is required to prevent oscillations. Larger output capacitors will be required for applications with large transient loads to limit peak voltage transients. See the Applications Information section for more information on output capacitance and reverse output characteristics. ADJ (Pin 4)/(Pin 5): Adjust. This is the input to the error amplifier. This pin is internally clamped to 7V. It has a bias current of 30nA which flows into the pin (see curve of ADJ Pin Bias Current vs Temperature in the Typical Performance Characteristics). The ADJ pin voltage is 1.24V referenced to ground, and the output voltage range is 1.24V to 60V. GND (Pins 5, 13)/(Pins 1, 6, 8, 9, 16, 17): Ground. The exposed backside of the package is an electrical connection for GND. As such, to ensure optimum device operation and thermal performance, the exposed pad must be connected directly to pin 5/pin 6 on the PC board. PWRGD (Pin 6)/(Pin 7): Power Good. The PWRGD flag is an open collector flag to indicate that the output voltage has come up to above 90% of the nominal output voltage. There is no internal pull-up on this pin; a pull-up resistor must be used. The PWRGD pin will change state from an open-collector to high impedance after both the output is above 90% of the nominal voltage and the capacitor on the CT pin has charged through a 1V differential. The maximum pull-down current of the PWRGD pin in the low state is 50A.
U
U
U
(DFN Package)/(TSSOP Package)
CT (Pin 7)/(Pin 10): Timing Capacitor. The CT pin allows the use of a small capacitor to delay the timing between the point where the output crosses the PWRGD threshold and the PWRGD flag changes to a high impedance state. Current out of this pin during the charging phase is 3A. The voltage difference between the PWRGD low and PWRGD high states is 1.6V (see the Applications Information Section). IN (Pins 10, 11)/(Pins 13,14): Input. Power is supplied to the device through the IN pin. A bypass capacitor is required on this pin if the device is more than six inches away from the main input filter capacitor. In general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in batterypowered circuits. A bypass capacitor in the range of 1F to 10F is sufficient. The LT3013B is designed to withstand reverse voltages on the IN pin with respect to ground and the OUT pin. In the case of a reversed input, which can happen if a battery is plugged in backwards, the LT3013B will act as if there is a diode in series with its input. There will be no reverse current flow into the LT3013B and no reverse voltage will appear at the load. The device will protect both itself and the load. NC (Pins 1, 8, 9, 12)/(Pins 2, 11, 12, 15): No Connect. No Connect pins may be floated, tied to IN or tied to GND.
3013bfa
7
LT3013B
APPLICATIO S I FOR ATIO
The LT3013B is a 250mA high voltage low dropout regulator with micropower quiescent current. The device is capable of supplying 250mA at a dropout voltage of 400mV. Operating quiescent current is only 65A. In addition to the low quiescent current, the LT3013B incorporates several protection features which make it ideal for use in battery-powered systems. The device is protected against both reverse input and reverse output voltages. In battery backup applications where the output can be held up by a backup battery when the input is pulled to ground, the LT3013B acts like it has a diode in series with its output and prevents reverse current flow. Adjustable Operation The LT3013B has an output voltage range of 1.24V to 60V. The output voltage is set by the ratio of two external resistors as shown in Figure 1. The device servos the output to maintain the voltage at the adjust pin at 1.24V referenced to ground. The current in R1 is then equal to 1.24V/R1 and the current in R2 is the current in R1 plus the ADJ pin bias current. The ADJ pin bias current, 30nA at 25C, flows through R2 into the ADJ pin. The output voltage can be calculated using the formula in Figure 1. The value of R1 should be less than 250k to minimize errors in the output voltage caused by the ADJ pin bias current. The adjustable device is tested and specified with the ADJ pin tied to the OUT pin and a 5A DC load (unless otherwise specified) for an output voltage of 1.24V. Specifications
Figure 1. Adjustable Operation
8
U
for output voltages greater than 1.24V will be proportional to the ratio of the desired output voltage to 1.24V; (VOUT/ 1.24V). For example, load regulation for an output current change of 1mA to 250mA is -7mV typical at VOUT = 1.24V. At VOUT = 12V, load regulation is: (12V/1.24V) * (-7mV) = -68mV Output Capacitance and Transient Response The LT3013B is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. A minimum output capacitor of 3.3F with an ESR of 3 or less is recommended to prevent oscillations. The LT3013B is a micropower device and output transient response will be a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. Bypass capacitors, used to decouple individual components powered by the LT3013B, will increase the effective output capacitor value. Extra consideration must be given to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and
IN VIN OUT R2 R1 LT3013B ADJ GND
3013 F01
W
UU
+
VOUT
VOUT = 1.24V 1 + R2 + (IADJ)(R2) R1 VADJ = 1.24V IADJ = 30nA AT 25C OUTPUT RANGE = 1.24V TO 60V
()
3013bfa
LT3013B
APPLICATIO S I FOR ATIO
temperature coefficients as shown in Figures 2 and 3. When used with a 5V regulator, a 16V 10F Y5V capacitor can exhibit an effective value as low as 1F to 2F for the DC bias voltage applied and over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. Care still must be exercised when using X5R and X7R capacitors; the X5R and X7R
20 0
CHANGE IN VALUE (%)
BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F X5R
-20 -40 -60 Y5V -80
-100
0
2
4
8 6 10 12 DC BIAS VOLTAGE (V)
14
16
3013 F02
Figure 2. Ceramic Capacitor DC Bias Characterics
40 20
CHANGE IN VALUE (%)
0 X5R -20 -40 -60 -80 Y5V
BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F -100 50 25 75 -50 -25 0 TEMPERATURE (C)
100
125
3013 F03
Figure 3. Ceramic Capacitor Temperature Characterics
U
codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. PWRGD Flag and Timing Capacitor Delay The PWRGD flag is used to indicate that the ADJ pin voltage is within 10% of the regulated voltage. The PWRGD pin is an open-collector output, capable of sinking 50A of current when the ADJ pin voltage is low. There is no internal pull-up on the PWRGD pin; an external pull-up resistor must be used. When the ADJ pin rises to within 10% of its final reference value, a delay timer is started. At the end of this delay, programmed by the value of the capacitor on the CT pin, the PWRGD pin switches to a high impedance and is pulled up to a logic level by an external pull-up resistor. To calculate the capacitor value on the CT pin, use the following formula:
C TIME = ICT * tDELAY VCT (HIGH) - VCT (LOW)
W
UU
Figure 4 shows a block diagram of the PWRGD circuit. At startup, the timing capacitor is discharged and the PWRGD pin will be held low. As the output voltage increases and the ADJ pin crosses the 90% threshold, the JK flip-flop is reset, and the 3A current source begins to charge the
3013bfa
9
LT3013B
APPLICATIO S I FOR ATIO
ADJ
+
J Q VCT(HIGH) - VBE (~1.1V)
VREF * 90%
-
Figure 4. PWRGD Circuit Block Diagram
timing capacitor. Once the voltage on the CT pin reaches the VCT(HIGH) threshold (approximately 1.7V at 25C), the capacitor voltage is clamped and the PWRGD pin is set to a high impedance state. During normal operation, an internal glitch filter will ignore short transients (<15s). Longer transients below the 90% threshold will reset the JK flip-flop. This flip-flop ensures that the capacitor on the CT pin is quickly discharged all the way to the VCT(LOW) threshold before restarting the time delay. This provides a consistent time delay after the ADJ pin is within 10% of the regulated voltage before the PWRGD pin switches to high impedance. Current Limit and Safe Operating Area Protection Like many IC power regulators, the LT3013B has safe operating area protection. The safe operating area protection decreases the current limit as the input voltage increases and keeps the power transistor in a safe operating region. The protection is designed to provide some output current at all values of input voltage up to the device breakdown (see curve of Current Limit vs Input Voltage in the Typical Performance Characteristics). The LT3013B is limited for operating conditions by maximum junction temperature. While operating at maximum input voltage, the output current range must be limited; when operating at maximum output current, the input voltage range must be limited. Device specifications will not apply for all possible combinations of input voltage and output current. Operating the LT3013B beyond the
10
-
+
U
ICT 3A CT PWRGD K VCT(LOW) ~0.1V
3013 F04
W
UU
maximum junction temperature rating may impair the life of the device. Thermal Considerations The power handling capability of the device will be limited by the maximum rated junction temperature (125C). The power dissipated by the device will be made up of two components: 1. Output current multiplied by the input/output voltage differential: IOUT * (VIN - VOUT) and, 2. GND pin current multiplied by the input voltage: IGND * VIN. The GND pin current can be found by examining the GND Pin Current curves in the Typical Performance Characteristics. Power dissipation will be equal to the sum of the two components listed above. The LT3013B series regulators have internal thermal limiting designed to protect the device during overload conditions. For continuous normal conditions the maximum junction temperature rating of 125C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices.
3013bfa
LT3013B
APPLICATIO S I FOR ATIO
The following tables list thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with one ounce copper.
Table 1. Measured Thermal Resistance (TSSOP)
COPPER AREA TOPSIDE 2500 sq mm 1000 sq mm 225 sq mm 100 sq mm BACKSIDE 2500 sq mm 2500 sq mm 2500 sq mm 2500 sq mm BOARD AREA 2500 sq mm 2500 sq mm 2500 sq mm 2500 sq mm THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 40C/W 45C/W 50C/W 62C/W
Table 2. Measured Thermal Resistance (DFN)
COPPER AREA TOPSIDE 2500 sq mm 1000 sq mm 225 sq mm 100 sq mm BACKSIDE 2500 sq mm 2500 sq mm 2500 sq mm 2500 sq mm BOARD AREA 2500 sq mm 2500 sq mm 2500 sq mm 2500 sq mm THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 40C/W 45C/W 50C/W 62C/W
The thermal resistance junction-to-case (JC), measured at the exposed pad on the back of the die, is 16C/W. Continuous operation at large input/output voltage differentials and maximum load current is not practical due to thermal limitations. Transient operation at high input/ output differentials is possible. The approximate thermal time constant for a 2500sq mm 3/32" FR-4 board with maximum topside and backside area for one ounce copper is 3 seconds. This time constant will increase as more thermal mass is added (i.e. vias, larger board, and other components). For an application with transient high power peaks, average power dissipation can be used for junction temperature calculations as long as the pulse period is significantly less than the thermal time constant of the device and board. Calculating Junction Temperature Example 1: Given an output voltage of 5V, an input voltage range of 8V to 12V, an output current range of 0mA to
U
250mA, and a maximum ambient temperature of 30C, what will the maximum junction temperature be? The power dissipated by the device will be equal to: IOUT(MAX) * (VIN(MAX) - VOUT) + (IGND * VIN(MAX)) where: IOUT(MAX) = 250mA VIN(MAX) = 12V IGND at (IOUT = 250mA, VIN = 12V) = 8mA So: P = 250mA * (12V - 5V) + (8mA * 12V) = 1.85W The thermal resistance will be in the range of 40C/W to 62C/W depending on the copper area. So the junction temperature rise above ambient will be approximately equal to: 1.85W * 50C/W = 92.3C The maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: TJMAX = 30C + 92.3C = 122.3C Example 2: Given an output voltage of 5V, an input voltage of 48V that rises to 72V for 5ms(max) out of every 100ms, and a 5mA load that steps to 200mA for 50ms out of every 250ms, what is the junction temperature rise above ambient? Using a 500ms period (well under the time constant of the board), power dissipation is as follows: P1(48V in, 5mA load) = 5mA * (48V - 5V) + (200A * 48V) = 0.23W P2(48V in, 50mA load) = 200mA * (48V - 5V) + (8mA * 48V) = 8.98W P3(72V in, 5mA load) = 5mA * (72V - 5V) + (200A * 72V) = 0.35W P4(72V in, 50mA load) = 200mA * (72V - 5V) + (8mA * 72V) = 13.98W
3013bfa
W
UU
11
LT3013B
APPLICATIO S I FOR ATIO
Operation at the different power levels is as follows: 76% operation at P1, 19% for P2, 4% for P3, and 1% for P4. PEFF = 76%(0.23W) + 19%(8.98W) + 4%(0.35W) + 1%(13.98W) = 2.03W With a thermal resistance in the range of 40C/W to 62C/W, this translates to a junction temperature rise above ambient of 81C to 125C. Protection Features The LT3013B incorporates several protection features which make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device is protected against reverse-input voltages, and reverse voltages from output to input. Current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. For normal operation, the junction temperature should not exceed 125C. The input of the device will withstand reverse voltages of 80V. No negative voltage will appear at the output. The device will protect both itself and the load. This provides protection against batteries which can be plugged in backward. The ADJ pin of the device can be pulled above or below ground by as much as 7V without damaging the device. If the input is left open circuit or grounded, the ADJ pin will act like an open circuit when pulled below ground, and like a large resistor (typically 100k) in series with a diode when pulled above ground. If the input is powered by a voltage source, pulling the ADJ pin below the reference voltage will cause the device to try and force the current limit current out of the output. This will cause the output to go to a unregulated high voltage. Pulling the ADJ pin above the reference voltage will turn off all output current. In situations where the ADJ pin is connected to a resistor divider that would pull the ADJ pin above its 7V clamp
REVERSE OUTPUT CURRENT (A)
12
U
voltage if the output is pulled high, the ADJ pin input current must be limited to less than 5mA. For example, a resistor divider is used to provide a regulated 1.5V output from the 1.24V reference when the output is forced to 60V. The top resistor of the resistor divider must be chosen to limit the current into the ADJ pin to less than 5mA when the ADJ pin is at 7V. The 53V difference between the OUT and ADJ pins divided by the 5mA maximum current into the ADJ pin yields a minimum top resistor value of 10.6k. In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage, or is left open circuit. Current flow back into the output will follow the curve shown in Figure 5. The rise in reverse output current above 7V occurs from the breakdown of the 7V clamp on the ADJ pin. With a resistor divider on the regulator output, this current will be reduced depending on the size of the resistor divider. When the IN pin of the LT3013B is forced below the OUT pin or the OUT pin is pulled above the IN pin, input current will typically drop to less than 2A. This can happen if the input of the LT3013B is connected to a discharged (low voltage) battery and the output is held up by either a backup battery or a second regulator circuit.
200 TJ = 25C 180 VIN = 0V VOUT = VADJ 160 140 120 100 80 60 40 20 0 0 1 2 345678 OUTPUT VOLTAGE (V) 9 10 CURRENT FLOWS INTO OUTPUT PIN ADJ PIN CLAMP (SEE ABOVE)
3013 F05
W
UU
Figure 5. Reverse Output Current
3013bfa
LT3013B
TYPICAL APPLICATIO S
LT3013B Automotive Application
IN 1F
NO PROTECTION DIODE NEEDED!
VIN 12V (LATER 42V)
+
VIN 48V (72V TRANSIENT)
1F
Constant Brightness for Indicator LED over Wide Input Voltage Range
RETURN
U
OUT LT3013B ADJ GND
249k
750k
3.3F
LOAD: CLOCK, SECURITY SYSTEM ETC
LT3013B Telecom Application
IN LT3013B
OUT
750k NO PROTECTION DIODE NEEDED!
249k
3013 TA05
+
3.3F
LOAD: SYSTEM MONITOR ETC
ADJ GND
-
BACKUP BATTERY
IN
OUT
LT3013B 1F GND -48V ILED = 1.24V/RSET -48V CAN VARY FROM -4V TO -80V ADJ RSET
3013 TA06
3.3F
3013bfa
13
LT3013B
PACKAGE DESCRIPTIO U
DE Package 12-Lead Plastic DFN (4mm x 3mm)
(Reference LTC DWG # 05-08-1695 Rev C)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 3.30 0.05 (2 SIDES) 0.50 BSC 4.00 0.10 (2 SIDES) R = 0.05 TYP 3.00 0.10 (2 SIDES) 1.70 0.05 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER 0.75 0.05 6 0.25 0.05 3.30 0.05 (2 SIDES) 1 0.50 BSC
(UE12/DE12) DFN 0905 REV C
3.60 0.05 1.70 0.05 2.20 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 0.40 0.10 12
7
PIN 1 TOP MARK (NOTE 6)
0.200 REF
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3013bfa
14
LT3013B
PACKAGE DESCRIPTIO U
FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
3.58 (.141)
4.90 - 5.10* (.193 - .201) 3.58 (.141) 16 1514 13 12 1110 9
6.60 0.10 4.50 0.10
SEE NOTE 4
2.94 (.116) 0.45 0.05 1.05 0.10 0.65 BSC 2.94 6.40 (.116) (.252) BSC
RECOMMENDED SOLDER PAD LAYOUT
12345678 1.10 (.0433) MAX
0 - 8
4.30 - 4.50* (.169 - .177)
0.25 REF
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE16 (BB) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3013bfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT3013B RELATED PARTS
PART NUMBER LT1020 DESCRIPTION 125mA, Micropower Regulator and Comparator COMMENTS VIN: 4.5V to 36V, VOUT = 2.5V, VDO = 0.4V, IQ = 40A, ISD = 40A, Comparator and Reference, Class B Outputs, S16, PDIP14 Packages VIN: 4.5V to 36V, VOUT = 2.5V, VDO = 0.4V, IQ = 40A, ISD = 10A, Comparator and Reference,Logic Shutdown, Ref Sources and Sinks 2/4mA, S8, N8 Packages VIN: 4.2V to 30/36V, VOUT = 3.75V, VDO = 0.42V, IQ = 30A, ISD = 16A, Reverse Battery Protection, SOT-223, S8, Z Packages VIN: 4.2V to 30V, VOUT = 3.75V, VDO = 0.4V, IQ = 50A, ISD = 16A, DD, S0T-223, S8,TO220-5, TSSOP20 Packages VIN: 3.6V to 25V, VOUT = 1.25V, IQ = 1.9mA, ISD = <1A, ThinSOT Package VIN: 7.4V to 60V, VOUT = 1.24V, IQ = 3.2mA, ISD = 2.5A, S8 Package VIN: 1.8V to 20V, VOUT = 1.22V, VDO = 0.3V, IQ = 20A, ISD = <1A, Low Noise < 20VRMS P-P, Stable with 1F Ceramic Capacitors, ThinSOT Package VIN: 1.8V to 20V, VOUT = 1.22V, VDO = 0.3V, IQ = 25A, ISD = <1A, Low Noise < 20VRMS P-P, MS8 Package VIN: 1.8V to 20V, VOUT = 1.22V, VDO = 0.3V, IQ = 30A, ISD = <1A, Low Noise < 20VRMS P-P, S8 Package VIN: 2.7V to 20V, VOUT = 1.21V, VDO = 0.34V, IQ = 1mA, ISD = <1A, Low Noise < 40VRMS P-P, "A" Version Stable with Ceramic Capacitors, DD, TO220-5 Packages VIN: 5.5V to 60V, VOUT = 1.20V, IQ = 2.5mA, ISD = 25A, TSSOP16/E Package VIN: 7.4V to 40V, VOUT = 1.24V, IQ = 3.2mA, ISD = 30A, N8, S8 Packages 90% Efficiency, VIN: 3.2V to 34V, VOUT = 1.25V, IQ = 14A, ISD = <1A, ThinSOT Package VIN: 5.5V to 60V, VOUT = 1.20V, IQ = 2.5mA, ISD = 25A, TSSOP16/E Package VIN: 1.8V to 20V, VOUT = 1.22V, VDO = 0.27V, IQ = 30A, ISD = <1A, Low Noise < 20VRMS P-P, MS8 Package VIN: 2.1V to 20V, VOUT = 1.21V, VDO = 0.34V, IQ = 1mA, ISD = <1A, Low Noise < 40VRMS P-P, "A" Version Stable with Ceramic Capacitors, DD, TO220-5, S0T-223, S8 Packages VIN: -1.9V to -20V, VOUT = -1.21V, VDO = 0.34V, IQ = 30A, ISD = 3A, Low Noise < 30VRMS P-P, Stable with Ceramic Capacitors, ThinSOT Package VIN: 3V to 80V, VOUT(MIN) = 1.2V, VDO = 0.3V, IQ = 30A, ISD < 1A, Low Noise: <100VRMS, Stable with 1F Output Capacitor, Exposed MS8E Package
LT1120/LT1120A 125mA, Micropower Regulator and Comparator
LT1121/ LT1121HV LT1129 LT1616 LT1676 LT1761 LT1762 LT1763
150mA, Micropower, LDO 700mA, Micropower, LDO 25V, 500mA (IOUT), 1.4MHz, High Efficiency Step-Down DC/DC Converter 60V, 440mA (IOUT), 100kHz, High Efficiency Step-Down DC/DC Converter 100mA, Low Noise Micropower, LDO 150mA, Low Noise Micropower, LDO 500mA, Low Noise Micropower, LDO
LT1764/LT1764A 3A, Low Noise, Fast Transient Response, LDO
LT1766 LT1776 LT1934/ LT1934-1 LT1956 LT1962
60V, 1.2A (IOUT), 200kHz, High Efficiency Step-Down DC/DC Converter 40V, 550mA (IOUT), 200kHz, High Efficiency Step-Down DC/DC Converter 300mA/60mA, (IOUT), Constant Off-Time, High Efficiency Step-Down DC/DC Converter 60V, 1.2A (IOUT), 500kHz, High Efficiency Step-Down DC/DC Converter 300mA, Low Noise Micropower, LDO
LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response, LDO
LT1964 LT3010
200mA, Low Noise Micropower, Negative LDO 50mA, High Voltage, Micropower LDO
3013bfa
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0306 REV A * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006

▲Up To Search▲

Price & Availability of LT3013B

	To Download LT3013B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .